1. Field of the Invention
The present invention generally relates to a semiconductor memory device for performing a refresh operation, and more specifically, to a technology for performing a refresh operation in an unlimited sense amplifier test mode.
2. Description of the Prior Art
Generally, a semiconductor memory device, which stores data in a plurality of memory cells or reads the stored data, comprises a plurality of bit lines, a plurality of word lines, a plurality of circuits for selecting the bit lines and the word lines, and a plurality of sense amplifiers.
FIG. 1 is a diagram illustrating a conventional semiconductor memory device.
The conventional semiconductor memory device comprises a mat 10 having a plurality of cells, two sense amplifiers 20 connected to one mat 10, a decoder 30, a separation control unit 40, a sensing control unit 50 and a sense amplifier enable unit 60.
The mat 10 comprises the plurality of cells connected to a plurality of word line WL and paired bit lines BL, BLB, and stores data in each cell.
The sense amplifier 20, which is connected between paired bit lines BL, BLB, senses and amplifies data in the paired bit lines BL, BLB in response to a sense amplifier enable signal SA_EN1.
The decoder 30 decodes a mat selecting signal MAT1 and a row address ADD, and outputs a word line selecting signal for selecting a word line WL of a cell.
The separation control unit 40 outputs separation control signals L1, R1, L2, R2 for controlling bit line separation transistors N1˜N4 in response to a mat enable signal MAT_EN from a sensing control unit 50.
The sensing control unit 50 receives the mat selecting signal MAT1, a clock enable signal CKE and a test mode signal TM, and outputs the mat enable signal MAT_EN.
The sense amplifier enable unit 60 receives a test mode signal TM, the mat selecting signal MAT1 and the clock enable signal CKE, and outputs the sense amplifier enable signal SA_EN1.
FIG. 2 is a circuit diagram illustrating the separation control unit 40 of FIG. 1.
The separation control unit 40 comprises a plurality of inverters IV1˜IV4.
The plurality of inverters IV1˜IV4 invert a plurality of mat enable signals MAT_EN0˜MAT_EN2, and outputs separation control signals R1, R2, L1, L2, respectively.
FIG. 3 is a circuit diagram illustrating the sensing control unit 50 of FIG. 1.
The sensing control unit 50 comprises an AND gate AND1, an inverter IV5 and a transmission unit 51.
The AND gate AND1 performs an AND operation on the mat selecting signal MAT1 and a signal obtained by inverting the clock enable signal CKE. The inverter IV5 inverts the test mode signal TM. The transmission unit 51, which comprises transmission gates T1 and T2 controlled by the test mode signal TM and an output signal from the inverter IV5, selectively outputs an output signal from the AND gate AND1 and the mat selecting signal MAT1 as the mat enable signal MAT_EN1.
FIG. 4 is a circuit diagram illustrating the sense amplifier enable unit 60 of FIG. 1.
The sense amplifier enable unit 60 comprises an AND gate AND2, an inverter IV6, a delay unit 61 and a transmission unit 62.
The AND gate AND2 performs an AND operation on the mat selecting signal MAT1 and a signal obtained by inverting the clock enable signal CKE. The inverter IV6 inverts the test mode signal TM, and the delay unit 61 delays and outputs the mat selecting signal MAT1.
The transmission unit 62, which comprises transmission gates T3 and T4 controlled by the test mode signal TM and an output signal from the inverter IV6, selectively outputs output signals from the AND gate AND2 and the delay unit 61 as the sense amplifier enable signal SA_EN1.
In the above-described semiconductor memory device, a micro-bridge is generated between a word line and a storage node or between a word line and a bit line during a general semiconductor process. As a result, an unlimited sense amplifier test mode is used to screen the micro-bridge.
More specifically, the unlimited sense amplifier test mode is a system to screen the micro-bridge between a word line and a storage node or between a word line and a bit line by sufficiently delaying sense amplifier driving start time while bit lines are kept being developed.
Hereinafter, the operation of the conventional semiconductor memory device at the normal mode and at the unlimited sense amplifier test mode is explained with reference to FIGS. 5a to 5c. 
First, at the normal mode, the transmission T2 of the sensing control unit 50 and the transmission gate T4 of the sensing control unit 60 are turned on by the test mode signal TM at a low level.
As a result, the transmission gate T2 outputs the mat selecting signal MAT1 at a high level as the mat enable signal MAT_EN1, and the transmission gate T4 outputs an output signal from the delay unit 61 as the sense amplifier enable signal SA_EN1. As shown in FIG. 5a, the sense amplifier enable signal SA_EN1 is delayed longer than the mat enable signal MAT_EN1, and enabled at a high level. Here, the separation control signals L1 and R2 become at a low level to turn off the bit line separation transistors N1 and N4.
As shown in FIG. 5a, at the normal mode, when the word line WL is enabled at a high level and the mat enable signal MAT_EN1 is enabled at a high level, the separation control signals L1 and R2 are disabled at a low level. If the separation control signals L1 and R2 are disabled at the low level, charges stored in the pair of bit lines and the cell are charge-shared. After a predetermined period, when the sense amplifier enable signal SA_EN1 is enabled at the high level, the sense amplifier 20 starts driving and then the pair of bit lines are developed. The development of the paired bit lines BL, BLB is to amplify a bit line BL to a core voltage VCORE level and a bit line bar BLB to a ground voltage VSS level.
Second, at the unlimited sense amplifier test mode, the transmission gate T1 of the sensing control unit 50 and the transmission gate T3 of the sensing control unit 60 are turned on by the test mode signal TM at a high level.
As a result, the transmission gate T1 outputs the output signal from the AND gate AND1 as the mat enable signal MAT_EN1, and the transmission gate T3 outputs the output signal from the AND gate AND2 as the sense amplifier enable signal SA_EN1.
Here, the AND gate AND1 performs an AND operation on the mat selecting signal MAT1 at the high level and a signal obtained by inverting the clock enable signal CKE at a low level, and outputs a low level signal. Then, when the clock enable signal CKE is disabled to a low level, the AND gate AND1 outputs a high level signal. That is, the mat enable signal MAT_EN1 is outputted at the low level when the clock enable signal CKE is at the high level, and enabled to the high level when the clock enable signal CKE is disabled to the low level. At the same time, the sense amplifier enable signal SA_EN1 is transited with the mat enable signal MAT_EN1.
As shown in FIG. 5b, at the unlimited sense amplifier test mode, when the word line WL is enabled to a high level and the clock enable signal CKE is disabled to the low level, the mat enable signal MAT_EN1 and the sense amplifier enable signal SA_EN1 are enabled to the high level, so that the sense amplifier 20 starts driving and then the pair of bit lines are developed.
Third, when a refresh operation is performed at the unlimited sense amplifier test mode, the unlimited sense amplifier test mode is required to be stopped to perform the refresh operation, since a refresh signal is not applied to the sensing control unit 50 and the sense amplifier enable unit 60.
In other words, when the refresh operation is performed at the unlimited sense amplifier test mode as shown in FIG. 5c, the sensing control unit 50 and the sense amplifier enable unit 60 are driven only at a test mode as at the unlimited sense amplifier test mode, and it is difficult to perform the refresh operation.